As computers have been developed to perform a greater number of instructions at greater speeds, many types of architectures have been developed to optimize this process. For example, a reduced instruction set computer (RISC) device uses fewer instructions in greater parallelism in executing those instructions to ensure that computational results will be available more quickly than the results provided by more traditional data processing systems. In addition to providing increasingly parallel execution of instructions, some data processing systems implement out-of-order instruction execution to increase processor performance. Out-of-order instruction execution increases processor performance by dynamically allowing instructions dispatched with no data dependencies to execute before previous instructions in an instruction stream that have unresolved data dependencies. In some data processing systems, instructions are renamed and instruction sequencing tables, also referred to as re-order buffers, facilitate out-of-order execution by re-ordering instruction execution at instruction completion time.
Re-order buffer devices are also used to allow speculative instruction execution. Therefore, data processing systems which support speculative instruction execution can be adapted for out-of-order execution with the addition of relatively minimal hardware. A portion of this added hardware includes logic which is used to determine a time and order that instructions should be issued. Such issue logic can be extremely complex since the dependencies and instructions in a state of a pipeline in which the instructions are being executed must be examined to determine a time at which the instruction should issue. If the issue logic is not properly designed, such issue logic can become a critical path for the data processing system and limit the frequency of instruction execution such that performance gains which could be achieved by out-of-order issue are eliminated.
The out-of-order instruction execution implemented by many prior art systems increases processor performance by dynamically allowing instructions dispatched with no data dependencies to execute before previous instructions in the instruction stream that have unresolved data dependencies. Register file renaming, renaming selected bits of architected facilities, for example registers accessible by software, and instruction sequencing tables (re-order buffers) facilitate out-of-order execution by re-ordering instruction execution at instruction completion time. For more information on such structures, refer to "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," by R. M. Tomasulo, published in IBM JOURNAL, January 1967, pp. 25-33. It should be noted that these devices are also used to allow speculative instruction execution. Therefore, system architecture supporting speculative instruction execution can be adapted for out-of-order execution with the addition of relatively "little" hardware and few overhead expenses. Thus, register file renaming may support out-of-order execution without modification from a speculative instruction execution architecture.
However, instructions that alter or use an architected register must be executed one at a time in a processor that includes only one such register. In these instances, data dependencies can only be resolved when the updating instruction completes, and the architected register then is valid. Logical operations that use or alter the contents of the condition register (CR) are representative of such instructions. The CR contains data values reporting on processor operations such as integer execution conditions, floating-point execution conditions, as well as user-defined condition values. Thus, when there is more than one instruction that updates or uses the CR, then those instructions must be executed in order according to the software program, and can cause bottlenecks in processor operations. For example, complex "IF" statements in source code can compile into multiple condition register logical instructions. According to the prior art, these must be serialized, because they all operate on the common, architected, CR.
Thus, there is a need in the art for a renaming apparatus and method that permits each instruction that needs to update or use the CR to execute out-of-order, thereby increasing instruction execution parallelism and processor performance.